Local project›Program blocks›Traffic Light Browser simulation
Program editor / LAD

Traffic Light

STOP20 ms scan
0 scans · 0 ms
Project explorer
Local PLCBrowser simulation · BOOL
Program blocks 8
Exercise library
Local simulationNo controller connected
Task / brief

Goal

Run an autonomous Red→Green→Yellow→Red cycle with fixed dwell times, and guarantee the lights are interlocked (never conflicting).

Inputs / outputs

NO physical button: released = 0
NC physical button: released = 1

Hints

Browse exercises

Main [LAD]Modified

Ladder diagram

LAD100%
Network 1
Stop (normal)Stop (normal)%I0.1StartStart%I0.0Stop (normal)Stop (normal)%I0.1RunningRunning%M0.0RunningRunning%M0.0
Properties coil · 2 paths
Contacts & branches
Path 1
1
2
Path 2
1
2
Output instruction
Q 0
Network 2
RunningRunning%M0.0Red phaseRed phase%M0.1T1T1TONINQPT 3000 msET 0 ms%M0.4
Properties TON · 1 path
Contacts & branches
Path 1
1
2
Output instruction
Q 0
Network 3
RunningRunning%M0.0Green phaseGreen phase%M0.2T2T2TONINQPT 2000 msET 0 ms%M0.5
Properties TON · 1 path
Contacts & branches
Path 1
1
2
Output instruction
Q 0
Network 4
RunningRunning%M0.0Yellow phaseYellow phase%M0.3T3T3TONINQPT 1000 msET 0 ms%M0.6
Properties TON · 1 path
Contacts & branches
Path 1
1
2
Output instruction
Q 0
Network 5
RunningRunning%M0.0T1 doneT1 done%M0.4T3 doneT3 done%M0.6Red phaseRed phase%M0.1T1 doneT1 done%M0.4RunningRunning%M0.0Red phaseRed phase%M0.1
Properties coil · 3 paths
Contacts & branches
Path 1
1
2
3
Path 2
1
2
Path 3
1
Output instruction
Q 0
Network 6
T1 doneT1 done%M0.4T2 doneT2 done%M0.5RunningRunning%M0.0Green phaseGreen phase%M0.2T2 doneT2 done%M0.5RunningRunning%M0.0Green phaseGreen phase%M0.2
Properties coil · 2 paths
Contacts & branches
Path 1
1
2
3
Path 2
1
2
3
Output instruction
Q 0
Network 7
T2 doneT2 done%M0.5T3 doneT3 done%M0.6RunningRunning%M0.0Yellow phaseYellow phase%M0.3T3 doneT3 done%M0.6RunningRunning%M0.0Yellow phaseYellow phase%M0.3
Properties coil · 2 paths
Contacts & branches
Path 1
1
2
3
Path 2
1
2
3
Output instruction
Q 0
Network 8
Red phaseRed phase%M0.1Red lightRed light%Q0.0
Properties coil · 1 path
Contacts & branches
Path 1
1
Output instruction
Q 0
Network 9
Green phaseGreen phase%M0.2Green lightGreen light%Q0.1
Properties coil · 1 path
Contacts & branches
Path 1
1
Output instruction
Q 0
Network 10
Yellow phaseYellow phase%M0.3Yellow lightYellow light%Q0.2
Properties coil · 1 path
Contacts & branches
Path 1
1
Output instruction
Q 0
10 networks · 12 tagsSelect a symbol to edit its properties
PLC tags / I/O table (12/64)

%I Input · %Q Output · %M Internal bit / byte.bit (0–7)

Address naming rules
AreaMeaningExample
%IInput%I0.0, %I0.1
%QOutput%Q0.0, %Q1.0
%MInternal bit%M0.0, %M0.1
  • Format: %areaByte.bit. Bytes: 0–65535; bits: 0–7. After %I0.7 comes %I1.0, not %I0.8.
  • Enter I1.2 or i1.2 to normalize to %I1.2. Addresses must match the direction and be unique.
  • Symbol names appear above ladder elements; addresses appear below. All contacts bound to a variable share its address.
  • These BOOL addresses are for simulation. The byte limit does not describe every physical CPU.
SymbolAddressDirectionTypeInitialLiveComment
StartBOOL0
StopOKBOOL1
runBOOL0
p1BOOL1
p2BOOL0
p3BOOL0
t1qBOOL0
t2qBOOL0
t3qBOOL0
RedBOOL1
GreenBOOL0
YellowBOOL0

Addresses are saved with the project. Existing tags keep their addresses when another tag is deleted. Exercise IDs keep their physical role.

Program valid
Unsaved changes
Simulation / live I/O

Device feedback

Stopped

Variable table

12
NameAddressValueControl
Start%I0.00
Stop (normal)%I0.11
Running%M0.00
Red phase%M0.11
Green phase%M0.20
Yellow phase%M0.30
T1 done%M0.40
T2 done%M0.50
T3 done%M0.60
Red light%Q0.01
Green light%Q0.10
Yellow light%Q0.20
Addresses are virtual teaching tags.
Diagnostics / verification6 cases

Test 1 of 6

Entire suite · isolated engines · results clear on edit

Test 1: Idle: Red on, others off

Click Run test to evaluate the entire suite.